I have some progress with FIFO.
Apparently I was not clearing RX_FIFO_RST and TX_FIFO_RST.
Now, I can see the FIFO address getting incremented with each write.
However, SDA is still silent and commands are not getting executed after I write 1 to I2C_TRANS_START.

I see. I have missed the reset bit. But even after added code to clear the reset bit (set and clear), it didn't make it work. I got the same result: got SCL and no SDA. PERIP_CLK_EN0: 0xf9c1e0ef PERIP_RST_EN0: 0x0 It seems something else is missing. Is the order of initialization steps is critical? ...

Thank you for your reply! I am new (or too old) to microcontrollers and may not understand all terminology. I do set I2C_CLK_EN to 1, and I can see SCL signal when enable it in idle mode with analyzer. Is this what you meant by "un-clockgated"? Not sure about reset. How do I check or take out of res...

Hi I am developing driver for I2C nodule of EXP32C3 using tinygo and having issue writing to the FIFO register. From the latest reference manual v0.5 it says 'In FIFO mode, the CPU writes to TX RAM via the fixed address I2C_DATA_REG, with addresses for writing in TX RAM incremented automatically by ...