Search found 3 matches
- Thu Feb 11, 2021 11:57 am
- Forum: General Discussion
- Topic: Dual Core access to memory
- Replies: 5
- Views: 5179
Re: Dual Core access to memory
I appreciate the help with my architecture but what I am trying to understand is really simple. We can ignore arrays and SPI because it's really about memory transactions at the hardware/firmware level and that is the way I should have framed my original question. In one core I have a task that writ...
- Wed Feb 10, 2021 11:04 pm
- Forum: General Discussion
- Topic: Dual Core access to memory
- Replies: 5
- Views: 5179
Re: Dual Core access to memory
So to expand. What is happening here is that I am detecting the position of a hand above a sensor array. My collector task (core) is collecting sensor data and writing it into a common array at the maximum rate it can be collected from a 100kHz SPI daisychain. Each position on the array is an analog...
- Wed Feb 10, 2021 1:19 pm
- Forum: General Discussion
- Topic: Dual Core access to memory
- Replies: 5
- Views: 5179
Dual Core access to memory
I have two tasks running constantly, one in each core. Both tasks access a common byte array. One task collects data via an SPI daisy chain and writes it into the array. It does this constantly. The other reads the data from the same array. It does not matter if the data is out of sync for a while s...