Search found 8 matches
- Tue Jan 10, 2023 10:51 pm
- Forum: ESP-IDF
- Topic: esp32 wroom always read 0s from ICS-43434
- Replies: 0
- Views: 718
esp32 wroom always read 0s from ICS-43434
I'm using ESP-WROOM with audio chip ICS-43434. Pins are attached: SCK to GPIO4, SD to GPIO36, WS to GPIO33. L/R is grounded. i2s_read() always returns 0s. I've tried many things, altering i2s_config but cannot get non-0. Am I dong something wrong? Maybe I can't use GPIO36? I'm using esp-idf v4.4.1. ...
- Sat Jan 18, 2020 6:10 pm
- Forum: ESP-IDF
- Topic: fast isr_handler during flash write or erase gives "Cache disabled but cached memory region accessed"
- Replies: 5
- Views: 6016
Re: fast isr_handler during flash write or erase gives "Cache disabled but cached memory region accessed"
Regarding, mcpwm_isr_register questions, I copied mcpwm_bldc_control example so I am calling ISR in IRAM_ATTR context:
mcpwm_isr_register(MCPWM_UNIT_0, isr_handler, NULL, ESP_INTR_FLAG_IRAM, NULL);
mcpwm_isr_register(MCPWM_UNIT_0, isr_handler, NULL, ESP_INTR_FLAG_IRAM, NULL);
- Tue Jan 14, 2020 12:03 am
- Forum: ESP-IDF
- Topic: fast isr_handler during flash write or erase gives "Cache disabled but cached memory region accessed"
- Replies: 5
- Views: 6016
Re: fast isr_handler during flash write or erase gives "Cache disabled but cached memory region accessed"
And it appears this happens with NVS reads too: DEBUG: tvocPPB: 0ppb ethanolRaw: 34063 Guru Meditation Error: Core 0 panic'ed (Cache disabled but cached memory region accessed) Core 0 register dump: PC : 0x40088d6b PS : 0x00060034 A0 : 0x80088de0 A1 : 0x3ffbf0e0 0x40088d6b: esp_cpu_stall at C:/msys3...
- Mon Jan 13, 2020 11:46 pm
- Forum: ESP-IDF
- Topic: fast isr_handler during flash write or erase gives "Cache disabled but cached memory region accessed"
- Replies: 5
- Views: 6016
fast isr_handler during flash write or erase gives "Cache disabled but cached memory region accessed"
We are using the example ISR handler for mcpwm esp-idf/examples/peripherals/mcpwm/mcpwm_bldc_control/main/mcpwm_bldc_control_hall_sensor_example.c CAP0 is setup on rising edge, and CAP1 on falling edge of a 910Hz signal. So we are getting interrupts every at a rate of 1.82Khz. Our main loop writes t...
- Wed Sep 18, 2019 8:49 pm
- Forum: Hardware
- Topic: WROVER and PSRAM and EMAC_TX_CLK
- Replies: 5
- Views: 7467
Re: WROVER and PSRAM and EMAC_TX_CLK
When you say "depends on your hardware design" do you refer to 1) GPIO0 as ethernet output will never work when using Wifi or Ble? 2) GPIO0 as ethernet output will never work with most ethernet RMII parts (like LAN8x70 series, etc). We are inverting the signal as shown in WROVER-B ESP32-Ethernet-Kit...
- Mon Sep 16, 2019 5:43 pm
- Forum: Hardware
- Topic: WROVER and PSRAM and EMAC_TX_CLK
- Replies: 5
- Views: 7467
Re: WROVER and PSRAM and EMAC_TX_CLK
Yes, I read that in latest v4.x release (it wasn't in rev 3.x which we used). But there is also this in WROVER-B kit which implies GPIO0 is fully supported in WROVER: ESP32-Ethernet-Kit V1.0 Getting Started Guide https://docs.espressif.com/projects/esp-idf/en/latest/hw-reference/get-started-ethernet...
- Fri Sep 13, 2019 5:44 am
- Forum: Hardware
- Topic: WROVER and PSRAM and EMAC_TX_CLK
- Replies: 5
- Views: 7467
Re: WROVER and PSRAM and EMAC_TX_CLK
As a follow on, it seems if I turn on Wifi or BLE, then ethernet becomes unstable. So GPIO0 with clock out does not work in hardware?
- Mon Sep 02, 2019 11:08 pm
- Forum: Hardware
- Topic: WROVER and PSRAM and EMAC_TX_CLK
- Replies: 5
- Views: 7467
WROVER and PSRAM and EMAC_TX_CLK
We are using WROVER-B and are using the extra PSRAM inside the WROVER-B package. And we need EMAC_TX_CLK output for our LAN8710A. We have a clock inverter between GPIO0 and LAN8710A CLKIN pin. We are using esp-idf (version v3.3-rc). When I try to initialize ethernet with clock mode ETH_CLOCK_GPIO0_O...